VHDL Code Examples for Altera DE1 FPGA

The following is a list of example synthesizable VHDL code for ERS 220 - Digital Design

Click one of the links below:

1. How to implement a 3-bit Adder in VHDL (For an Altera FPGA utilizing a 7-segment display)
2. Implementation of an 8-bit Hamming code error-detecting decoder on an Altera FPGA
3. A classic - Implementing Ping Pong game on an Altera DE-1 FPGA