Implementation of an 8-bit Hamming code error-detecting decoder on an Altera FPGA

Background:

The system takes a potentially corrupted 8-bit Hamming code as input and at its output will display a diagnosis of the error which occurred in transmission. The encoded binary word contains four data bits and four redundancy (parity-check) bits. The code is defined by a parity-check matrix:

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VHDL Implementation on an Altera DE1 FPGA:

library ieee;
use ieee.std_logic_1164.all;

entity ERSPrac2 is
port (
  LEDG : OUT std_logic_vector(7 DOWNTO 0);
  LEDR : OUT std_logic_vector(9 DOWNTO 0);
  SW : IN std_logic_vector(9 DOWNTO 0);
  
  
  HEX0 : OUT std_logic_vector(6 DOWNTO 0);
  HEX1 : OUT std_logic_vector(6 DOWNTO 0);
  HEX2 : OUT std_logic_vector(6 DOWNTO 0);
  HEX3 : OUT std_logic_vector(6 DOWNTO 0)
  );
  
end ERSPrac2;

architecture behave of ERSPrac2 is
  signal pg1out : std_logic := '0';
  signal pg2out : std_logic := '0';
  signal pg3out : std_logic := '0';
  signal pg4out : std_logic := '0';
  
  signal syndrome : std_logic_vector(3 downto 0);
  signal BCDout : std_logic_vector(3 downto 0);
  
  --signal input : std_logic_vector(7 downto 0);

begin

 PROCESS(SW(9)) is
  --variable c_zero : std_logic := '0'
 begin
 
 if (SW(9) = '1') then
 
  -- load the states of switches into red leds for aesthetics
  LEDR(7 downto 0) <= SW(7 downto 0);
  
  -- parity generators according to matrix H
  pg1out <= SW(7) XOR SW(2) XOR SW(1) XOR SW(0);
  pg2out <= SW(6) XOR SW(3) XOR SW(1) XOR SW(0);
  pg3out <= SW(5) XOR SW(3) XOR SW(2) XOR SW(0);
  pg4out <= SW(4) XOR SW(3) XOR SW(2) XOR SW(1);
  
  --LEDG(3) <= pg1out;
  --LEDG(2) <= pg2out;
  --LEDG(1) <= pg3out;
  --LEDG(0) <= pg4out;
  
  syndrome(3) <= pg1out;
  syndrome(2) <= pg2out;
  syndrome(1) <= pg3out;
  syndrome(0) <= pg4out;
  
  LEDG(3 DOWNTO 0) <= syndrome(3 DOWNTO 0);
  
  -- at this point, syndrome vector is in syndrome signal vector.
  
  CASE syndrome IS
   WHEN "0000"=>BCDout<="1001";
   WHEN "0001"=>BCDout<="0100";
   WHEN "0010"=>BCDout<="0101";
   WHEN "0100"=>BCDout<="0110";
   WHEN "0111"=>BCDout<="0011";
   WHEN "1000"=>BCDout<="0111";
   WHEN "1011"=>BCDout<="0010";   
   WHEN "1101"=>BCDout<="0001";
   WHEN "1110"=>BCDout<="0000";
   
   WHEN OTHERS=>BCDout<="1000";
  END CASE;
   
  -- at this point we have the syndrome vector converted into a BCD type output in signal BCDout
  -- now display the BCDout in hex0.
  
  CASE BCDout IS
    WHEN "0000"=>HEX0<="1000000";
    WHEN "0001"=>HEX0<="1111001";
    WHEN "0010"=>HEX0<="0100100";
    WHEN "0011"=>HEX0<="0110000";
    WHEN "0100"=>HEX0<="0011001";
    WHEN "0101"=>HEX0<="0010010";
    WHEN "0110"=>HEX0<="0000010";
    WHEN "0111"=>HEX0<="1111000";
    WHEN "1000"=>HEX0<="0000000";
    WHEN "1001"=>HEX0<="0011000";
    WHEN "1010"=>HEX0<="0001000"; -- A
    WHEN "1011"=>HEX0<="0000011"; -- B
    WHEN "1100"=>HEX0<="0100111"; -- C
    WHEN "1101"=>HEX0<="0100001"; -- d
    WHEN "1110"=>HEX0<="0000110"; -- e
    WHEN OTHERS=>HEX0<="1111111";
  END CASE;
  
  
 else
 
  HEX0 <= (others => '1');
  HEX1 <= (others => '1');
  HEX2 <= (others => '1');
  HEX3 <= (others => '1');
  
  LEDG(7 DOWNTO 0) <= (others => '0');
  LEDR(9 DOWNTO 0) <= (others => '0');
 
 end if;
 
 end process;
 
end behave;